Nexperia USA Inc. PUMD3,135

Overview

PUMD3 from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, integrating two complementary bias-resistor transistors - TR1 (NPN) and TR2 (PNP) - with R1 = 10 kΩ and R2 = 10 kΩ per channel, rated for 50 V V_CEO, 100 mA output current, and operating across −65 °C to +150 °C ambient. It serves as a compact, dual-polarity switching element in digital control circuits requiring matched input thresholds and reduced external component count.

For engineers reviewing the PUMD3 datasheet, PUMD3 pinout, PUMD3 application, or PUMD3 equivalent, this device is selected for cost-sensitive digital switching where integrated base resistors eliminate discrete bias networks, simplify PCB layout, and support automotive and industrial logic-level interfacing with verified VI(on)/VI(off) thresholds and thermal derating up to 300 mW total device power dissipation.

Technical Context

The PUMD3 integrates two monolithically matched transistors on a single die: TR1 is an NPN transistor with typical f_T = 230 MHz and h_FE ≥ 30 at I_C = 5 mA; TR2 is its complementary PNP counterpart with f_T = 180 MHz and identical R1/R2 = 1.0 ±0.2 ratio. Both channels share independent base resistors enabling direct microcontroller GPIO drive without external pull-up/down components.

Its dual-transistor architecture supports push-pull or complementary switching topologies with symmetrical input voltage thresholds: VI(on) = 1.8–2.5 V (TR1) and −1.8 to −2.5 V (TR2), while VI(off) remains ≤ ±0.8 V, ensuring robust noise immunity in 3.3 V and 5 V logic systems. Thermal resistance is 417 K/W (junction-to-ambient, per device on FR4 PCB), supporting stable operation under continuous 100 mA load conditions.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package: 1.3 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, designed for reflow soldering with defined wave/thermal profiles per Figures 20–21.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMH11 and PUMB11, the PUMD3 uniquely provides matched NPN+PNP functionality in one package-enabling true complementary switching without inter-channel timing skew or layout mismatch, making it irreplaceable in bidirectional signal control and rail-to-rail logic translation.

Availability

PUMD3 is available at Aetrix Electronics and suitable for automotive body electronics, industrial programmable logic controllers, and consumer appliance power sequencing requiring stable component supply and long-term production continuity.

Supply support for PUMD3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors for automotive, industrial, mobile, and computing markets.

The PUMD3 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace legacy discrete BJT + resistor combinations in cost- and space-constrained digital interface applications.

FAQ

What is the maximum allowable junction temperature for continuous operation?

The absolute maximum junction temperature (T_j) is 150 °C per the datasheet limiting values table. Operation must remain within this limit under all ambient and power conditions; derating begins at 25 °C ambient, with total device power dropping linearly to zero at 150 °C junction temperature as shown in Figure 1.

Can PUMD3 be used in 3.3 V logic systems without level shifters?

Yes - VI(on) is specified as 1.8–2.5 V for TR1 and −1.8 to −2.5 V for TR2, and VI(off) ≤ ±0.8 V, providing >1.0 V noise margin against 3.3 V logic thresholds. The built-in resistors ensure proper base biasing without external components, making it directly compatible with 3.3 V GPIOs.

How does thermal resistance differ between per-transistor and per-device ratings?

R_th(j-a) is 625 K/W per transistor (isolated operation) but improves to 417 K/W for the full device on FR4 PCB due to shared thermal mass and copper plane coupling. This means total 300 mW dissipation is achievable only when both transistors operate simultaneously under defined board layout conditions.

Is there a recommended PCB footprint for automated assembly?

Yes - Nexperia specifies two footprints: reflow soldering uses a 2.65 mm × 2.35 mm pad layout with 0.5 mm wide pads (4×) and 0.6 mm spacing (2×), while wave soldering requires a 5.3 mm × 2.45 mm layout with preferred transport direction aligned to Pin 1 index. Both are detailed in Figures 20 and 21 of the datasheet.