Nexperia USA Inc. PUMD3-QZ

Overview

PUMD3-QZ from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT363-3 (TSSOP6) package, with built-in 10 kΩ input bias resistors (R1 = R2 = 10 kΩ), 50 V V_CEO, 100 mA output current per transistor, and AEC-Q101 qualification for automotive digital switching applications such as IC input control and load switching.

For engineers reviewing the PUMD3-QZ datasheet, PUMD3-QZ pinout, PUMD3-QZ application, or PUMD3-QZ equivalent, this device serves as a space- and BOM-optimized alternative to discrete BC847-Q/BC857-Q pairs in cost-sensitive, high-reliability digital interface circuits requiring matched NPN/PNP switching with integrated biasing.

Technical Context

This dual-transistor device implements two independent, resistor-equipped BJTs - TR1 (NPN) and TR2 (PNP) - sharing no internal connection between transistors except common ground terminals. Each transistor features dedicated base-input pins with integrated R1/R2 bias networks enabling direct logic-level drive without external resistors.

The device operates under ±10 V input voltage limits (TR1: −10 V to +10 V; TR2: −40 V to +10 V), supports DC current gain (h_FE) ≥30 at 5 mA collector current, and delivers ≤100 mV V_CE(sat) at I_C = 10 mA / I_B = 0.5 mA (TR1) and comparable saturation performance for TR2 under negative polarity conditions.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package with 0.65 mm pitch, 2.2 mm × 1.35 mm body size, and exposed pad-compatible footprint per Nexperia's reflow soldering guidelines (Fig. 20).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with PUMD3-QZ, PUMH11-Q and PUMB11-Q offer identical resistor values and thermal performance but lack the mixed-polarity architecture essential for true complementary switching - making PUMD3-QZ uniquely suited for level translation, push-pull drivers, and bidirectional interface circuits.

Availability

PUMD3-QZ is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC I/O modules, and consumer appliance motor control requiring stable component supply, long-term lifecycle support, and AEC-Q101-compliant sourcing.

Supply support for PUMD3-QZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.

The PUMD3-QZ belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered to simplify digital interface design by integrating biasing networks into miniature packages for space-constrained, high-reliability applications.

FAQ

What is the maximum operating temperature for PUMD3-QZ?

The PUMD3-QZ has a maximum junction temperature (T_j) of 150 °C and an ambient operating range of −65 °C to +150 °C. Its thermal resistance from junction to ambient is 417 K/W on FR4 PCB, allowing full 100 mA output current at ambient temperatures up to +85 °C with natural convection cooling.

Can PUMD3-QZ replace BC847-Q and BC857-Q simultaneously?

Yes - PUMD3-QZ integrates one NPN (equivalent to BC847-Q) and one PNP (equivalent to BC857-Q) in a single SOT363-3 package with matching bias resistors, enabling direct substitution in digital switching applications while reducing PCB area, assembly steps, and BOM line items by 50% compared to using two separate RETs.

What is the meaning of the marking code 'D%3' on PUMD3-QZ?

The top-side marking 'D%3' identifies the device as PUMD3-QZ, where 'D' denotes the product family, '%' is a placeholder for the manufacturing site code (e.g., 'A' for Nijmegen, 'B' for Bangkok), and '3' indicates the specific variant within the PUMD series - fully traceable to Nexperia's lot and wafer-level process data.

Does PUMD3-QZ support 1.8 V logic-level drive?

No - the minimum recommended VI(on) for TR1 (NPN) is 1.8 V at I_C = 10 mA, and VI(off) is 1.1 V max; driving reliably at 1.8 V logic requires margin above VI(on) and may result in partial turn-on or increased V_CE(sat). It is optimized for 3.3 V or 5 V CMOS/TTL interfaces, not sub-2 V logic families.