Nexperia USA Inc. PUMD48,125

Overview

PUMD48 from Nexperia is a dual resistor-equipped transistor (RET) integrating one NPN and one PNP silicon transistor in a single SOT363-3 (TSSOP6) package, rated for 50 V V_CEO, 100 mA output current per transistor, with built-in bias resistors R1 = 47 kΩ / R2 = 47 kΩ (TR1, NPN) and R1 = 2.2 kΩ / R2 = 47 kΩ (TR2, PNP); used for low-current digital interface buffering and IC input control in space-constrained consumer and industrial PCBs.

For engineers reviewing the PUMD48 datasheet, PUMD48 pinout, PUMD48 application, or PUMD48 equivalent, this page delivers verified electrical parameters, validated pin functions, confirmed thermal derating curves, and real-world use cases for discrete logic-level signal translation and bidirectional peripheral driving - not generic switching or power control.

Technical Context

The PUMD48 implements two independent bipolar junction transistors on one die: TR1 is an NPN RET with R1 = 47 kΩ (input bias), R2 = 47 kΩ (base-emitter feedback), and R2/R1 = 1.0 ±0.2; TR2 is a PNP RET with R1 = 2.2 kΩ, R2 = 47 kΩ, and R2/R1 = 21 ±5. Both transistors share common ground terminals but operate with opposite polarity and distinct input voltage thresholds (VI(on) = 1.6–3.0 V for TR1; −0.75 to −1.1 V for TR2).

Each transistor supports DC current gain h_FE ≥ 80 (TR1 at I_C = 5 mA) and ≥ 100 (TR2 at I_C = −10 mA), collector-emitter saturation voltage ≤ 100 mV (TR1) or ≤ −100 mV (TR2), and transition frequency f_T = 230 MHz (TR1) / 180 MHz (TR2), enabling reliable operation up to mid-frequency digital switching (≤10 MHz) without external biasing components.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mount package: 1.35 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, lead-free and RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with NSVDU2D143XZ and EMX11T2R, PUMD48 uniquely balances low-input-current NPN drive (55 µA), high-gain PNP stage (h_FE ≥100), and matched thermal resistance (417 K/W), making it optimal for battery-powered or thermally constrained dual-signal interface designs.

Availability

PUMD48 is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, digital input level shifting, and legacy logic compatibility bridging requiring stable component supply across production lifecycles.

Supply support for PUMD48 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.

The PUMD48 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce component count and simplify digital interface design in compact, cost-sensitive embedded systems.

FAQ

What is the maximum continuous current each transistor in the PUMD48 can handle?

The PUMD48 supports 100 mA continuous output current per transistor (TR1 and TR2) under conditions defined in Table 5 of the datasheet, with derating applied above Tamb = 25 °C per the 300 mW total device power limit and 417 K/W thermal resistance. At 70 °C ambient, maximum usable current drops to ≈75 mA per transistor to maintain Tj ≤ 150 °C.

Can the PUMD48 be used to replace two separate SOT23 transistors in a push-pull configuration?

Yes - the integrated NPN (TR1) and PNP (TR2) pair with shared ground pins (GND1/GND2) and complementary input thresholds enables true push-pull operation without cross-conduction risk. Pin 2 (I1) and Pin 5 (I2) accept independent logic signals, while Pins 6 (O1) and 3 (O2) provide sourcing and sinking outputs referenced to their respective emitters, supporting rail-to-rail switching in compact layouts.

Does the PUMD48 require external pull-up or pull-down resistors on its input pins?

No - the built-in R1 and R2 bias resistors eliminate the need for external base resistors. For TR1 (NPN), I1 is internally pulled to GND1 through R1 = 47 kΩ, and for TR2 (PNP), I2 is internally pulled to GND2 through R1 = 2.2 kΩ. This allows direct connection to CMOS/TTL outputs without additional components, provided drive voltage meets VI(on)/VI(off) thresholds.

How does thermal performance differ between per-transistor and per-device power ratings?

The datasheet specifies 200 mW per transistor (400 mW theoretical max) but limits total device dissipation to 300 mW. This reflects shared thermal path: simultaneous conduction in both transistors raises junction temperature faster than either alone. Derating follows the per-device curve in Figure 1 - at 70 °C ambient, usable power is ≈180 mW total, meaning combined TR1+TR2 power must stay below that value regardless of individual current distribution.