Nexperia USA Inc. PUMD48,165

Overview

PUMD48 from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT363-3 (TSSOP6) package, rated for 50 V V_CEO, 100 mA output current per transistor, with built-in bias resistors R1 = 47 kΩ / R2 = 47 kΩ (TR1, NPN) and R1 = 2.2 kΩ / R2 = 47 kΩ (TR2, PNP); used for compact digital logic interfacing and low-current peripheral control.

For engineers reviewing the PUMD48 datasheet, PUMD48 pinout, PUMD48 application, or PUMD48 equivalent, this device serves as a space-saving, component-count-reducing replacement for discrete NPN+PNP pairs in level-shifting, bus buffering, and IC input driving circuits where bias network integration and thermal efficiency on FR4 PCBs are critical selection criteria.

Technical Context

The PUMD48 implements two independent RET structures: TR1 (NPN) features R1 = 47 kΩ ±28% and R2/R1 = 1.0 ±0.2, enabling direct TTL/CMOS-compatible switching with VI(on) = 1.6–3.0 V and VI(off) = 0.8–1.2 V; TR2 (PNP) uses R1 = 2.2 kΩ ±30% and R2/R1 = 21 ±5, delivering negative-input logic compatibility with VI(on) = −0.75 to −1.1 V and VI(off) = −0.5 to −0.6 V.

Each transistor operates within IEC 60134 absolute maximum ratings: V_CEO = 50 V, I_O = 100 mA, T_j ≤ 150 °C; thermal resistance is 417 K/W (per device, FR4 PCB), supporting continuous operation up to 300 mW total power dissipation at 25 °C ambient.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) surface-mount plastic package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height; optimized for reflow soldering with defined solder paste land pattern (2.65 mm × 2.35 mm).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with NSVD2001MW6T1G and EMX12T2R, the PUMD48 uniquely delivers matched NPN+PNP characteristics in one die, enabling true push-pull output stages, bidirectional bus termination, and reduced interconnect inverter count-critical for minimizing propagation delay and PCB layer count in compact digital systems.

Availability

PUMD48 is available at Aetrix Electronics and suitable for industrial I/O modules, smart sensor nodes, and embedded HMI panels requiring stable component supply, long-lifecycle assurance, and consistent parametric performance across production batches.

Supply support for PUMD48 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable components for automotive, industrial, mobile, and computing applications.

The PUMD48 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically for digital interface simplification in space- and cost-sensitive embedded systems where reducing passive component count and improving assembly yield are primary design goals.

FAQ

What is the maximum safe operating voltage for each transistor in the PUMD48?

The absolute maximum collector-emitter voltage (V_CEO) is 50 V for both TR1 (NPN) and TR2 (PNP), as defined in IEC 60134 limiting values. Operation above this voltage risks permanent breakdown. Recommended working voltage is ≤30 V to maintain 40% safety margin under transient conditions and temperature variation.

Can the PUMD48 replace two discrete BC847/BC857 transistors in a logic inverter pair?

Yes - the PUMD48 directly replaces one BC847 (NPN) and one BC857 (PNP) with integrated bias resistors, eliminating four external resistors. Its VI(on)/VI(off) thresholds and h_FE ≥80 ensure equivalent switching behavior at 3.3 V/5 V logic levels, and its matched thermal characteristics prevent drift-induced timing skew between channels.

Is the GND1 and GND2 pin electrically isolated inside the package?

No - GND1 and GND2 are separate terminals but connect to the same internal substrate potential; they are not galvanically isolated. They must be connected to the same system ground plane. Separation enables flexible PCB routing and avoids shared emitter impedance in high-frequency layouts, but does not provide isolation.

Does the PUMD48 support PWM dimming of LEDs at frequencies above 1 kHz?

Yes - with f_T = 230 MHz (TR1) and 180 MHz (TR2), the PUMD48 supports clean switching up to 50 MHz. At 1–10 kHz PWM, it achieves <100 ns rise/fall times and <20 ns channel skew, ensuring minimal duty-cycle distortion and consistent brightness control across dual LED channels.