Nexperia USA Inc. PUMD48-QX

Overview

PUMD48-QX from Nexperia is an NPN/PNP resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, integrating two bias-resistor-configured transistors: TR1 (NPN, R1 = 47 kΩ, R2 = 47 kΩ) and TR2 (PNP, R1 = 2.2 kΩ, R2 = 47 kΩ). It delivers 100 mA output current per transistor, supports ±50 V V_CEO, and is AEC-Q101 qualified for automotive signal-level switching.

For engineers reviewing the PUMD48-QX datasheet, PUMD48-QX pinout, PUMD48-QX application, or PUMD48-QX equivalent, this device serves as a space- and BOM-optimized replacement for discrete NPN+PNP pairs in digital logic interfacing, low-current peripheral drivers, and IC input control circuits where built-in biasing eliminates external resistors.

Technical Context

This dual RET combines an NPN transistor with h_FE ≥ 80 at I_C = 5 mA and V_CE = 5 V, and a PNP transistor with h_FE ≥ 100 at I_C = −10 mA and V_CE = −5 V. Both transistors feature integrated base bias networks enabling direct TTL/CMOS-level drive without external resistors.

The TR1 NPN has V_I(on) = 1.6–3.0 V and V_I(off) = 0.8–1.2 V; TR2 PNP has V_I(on) = −0.75 to −1.1 V and V_I(off) = −0.6 to −0.5 V - ensuring robust noise margin and predictable switching thresholds across −40 °C to +150 °C ambient.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package, 1.3 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height, designed for reflow and wave soldering per JEDEC standards.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual RET applications.

Compared with NSVD20011MUTBG and EMH11T2R, PUMD48-QX uniquely integrates matched yet asymmetric NPN/PNP bias networks - enabling true complementary switching in one AEC-Q101-qualified package while minimizing GPIO loading and PCB real estate.

Availability

PUMD48-QX is available at Aetrix Electronics and suitable for automotive door modules, industrial PLC input stages, consumer appliance UI panels, and medical diagnostic instrument I/O requiring stable component supply, long-lifecycle support, and AEC-Q101 compliance.

Supply support for PUMD48-QX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices optimized for efficiency-critical applications.

PUMD48-QX belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to reduce design complexity and improve reliability in automotive and industrial digital interface circuits.

FAQ

What is the maximum operating junction temperature for PUMD48-QX?

The absolute maximum junction temperature is 150 °C, validated per AEC-Q101 stress testing. Derating begins above 25 °C ambient, with total device power dissipation limited to 300 mW at T_amb ≤ 25 °C on standard FR4 PCB. Thermal resistance from junction to ambient is 417 K/W in free air.

Can PUMD48-QX replace two separate SOT23 transistors in existing designs?

Yes - its 6-pin SOT363-3 footprint replaces two SOT23-3 devices plus four external bias resistors. Pin compatibility requires mapping: TR1 emitter (GND1) and collector (O1) align with standard NPN SOT23 pinout; TR2 emitter (GND2) and collector (O2) follow PNP SOT23 convention. Layout review is recommended due to shared ground separation.

Does PUMD48-QX support 3.3 V logic-level drive directly?

Yes - TR1's V_I(on) ranges from 1.6 V to 3.0 V and TR2's from −0.75 V to −1.1 V, making both transistors fully compatible with 3.3 V CMOS/TTL outputs. No level-shifting circuitry is needed, and the built-in R1 values ensure sufficient base current for full saturation at 3.3 V drive.

How does the asymmetric R1 ratio between TR1 and TR2 benefit circuit design?

The TR1 NPN uses R1 = 47 kΩ for low-input-current drive (ideal for weak GPIOs), while TR2 PNP uses R1 = 2.2 kΩ to deliver higher base current for faster turn-on and lower V_CE(sat) under sink loads. This asymmetry enables balanced rise/fall times in push-pull configurations without external resistor tuning.