Nexperia USA Inc. PUMD48/ZLH

Overview

PUMD48/ZLH from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP bipolar junction transistor in a single SOT363-3 (TSSOP6) package, rated for 50 V V_CEO, 100 mA output current per transistor, with built-in bias resistors R1 = 47 kΩ / R2 = 47 kΩ (TR1, NPN) and R1 = 2.2 kΩ / R2 = 47 kΩ (TR2, PNP); used for compact digital signal inversion and level translation in space-constrained logic interface circuits.

For engineers reviewing the PUMD48/ZLH datasheet, PUMD48/ZLH pinout, PUMD48/ZLH application, or PUMD48/ZLH equivalent, this device serves as a dual-polarity, resistor-biased switching pair optimized for low-current peripheral control, IC input driving, and discrete transistor replacement in 3.3 V/5 V logic systems - requiring no external base resistors and enabling direct microcontroller GPIO interfacing.

Technical Context

The PUMD48/ZLH implements two independent BJT structures: TR1 is an NPN transistor with integrated 47 kΩ input resistor (R1) and matched 47 kΩ feedback resistor (R2), yielding R2/R1 ≈ 1.0; TR2 is a complementary PNP transistor with 2.2 kΩ R1 and 47 kΩ R2, delivering R2/R1 ≈ 21. Both transistors share common ground terminals but operate with opposite polarity, supporting push-pull or complementary switching topologies without external bias networks.

Each transistor exhibits verified DC current gain (h_FE) of ≥80 (TR1, I_C = 5 mA) and ≥100 (TR2, I_C = −10 mA), collector-emitter saturation voltage ≤100 mV (TR1) and ≤−100 mV (TR2), and on-state input voltage thresholds of 1.6–3.0 V (TR1) and −0.75 to −1.1 V (TR2), enabling robust TTL/CMOS-compatible switching across industrial temperature range (−65 °C to +150 °C).

Key Specifications

Pinout & Package

Package: SOT363-3 (TSSOP6), 6-pin surface-mount plastic package with 0.65 mm pitch, 2.2 mm × 1.35 mm footprint, and exposed pad not present - suitable for reflow and wave soldering per IPC-7351B.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resistor-equipped transistor applications.

Compared with NSVDU2D12TZ and EMX13T2R, PUMD48/ZLH uniquely delivers matched NPN+PNP functionality in one package with asymmetric bias ratios optimized for complementary switching - reducing component count by two transistors and four resistors versus dual-single RET solutions.

Availability

PUMD48/ZLH is available at Aetrix Electronics and suitable for industrial control interfaces, embedded sensor subsystems, and consumer electronics logic translation requiring stable component supply, long-term manufacturability, and RoHS-compliant packaging.

Supply support for PUMD48/ZLH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components - including logic, discretes, MOSFETs, and ESD protection - with manufacturing rooted in process consistency and automotive-grade reliability standards.

PUMD48/ZLH belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically for reducing design complexity in digital interface and peripheral driver applications where space, assembly cost, and signal integrity are critical constraints.

FAQ

What is the maximum safe operating voltage for each transistor in PUMD48/ZLH?

The absolute maximum collector-emitter voltage (V_CEO) is 50 V for both TR1 (NPN) and TR2 (PNP) under open-base conditions, as confirmed in Table 5 (Limiting Values). Operation above this rating risks permanent breakdown. For reliable long-term use, design should limit V_CE to ≤30 V under load, especially at elevated temperatures where leakage increases.

Can PUMD48/ZLH be used in analog amplifier configurations?

No - PUMD48/ZLH is designed exclusively for digital switching applications. Its integrated bias resistors fix the base current path, preventing external bias network customization required for linear amplification. The specified h_FE values apply only under switching conditions (V_CE = 5 V or −5 V), and f_T performance is characterized for RF switching, not small-signal gain stability.

How does the R2/R1 ratio affect switching behavior in TR2 (PNP)?

TR2's R2/R1 ratio of 21 ±24% ensures strong negative feedback that maintains cutoff when I2 is near 0 V and guarantees deep saturation when driven sufficiently negative (e.g., −0.75 V). This high ratio improves noise immunity and prevents partial turn-on due to leakage or crosstalk - critical for reliable operation in noisy industrial environments.

Is thermal derating required when operating PUMD48/ZLH at 100 mA continuous current?

Yes - at full 100 mA per transistor (200 mA total device current), power dissipation exceeds 200 mW even at room temperature. Per Figure 1, the device's per-device P_tot derates linearly above 25 °C ambient; at 75 °C, max allowable power drops to ~150 mW. For continuous 100 mA operation, heatsinking or airflow is recommended above 50 °C ambient.