Nexperia USA Inc. PUMD48/ZLX

Overview

PUMD48/ZLX from Nexperia is a resistor-equipped double transistor (RET) integrating one NPN and one PNP silicon transistor in a single SOT363-3 (SC-88/TSSOP6) package, rated for 50 V V_CEO, 100 mA output current per transistor, with built-in bias resistors R1 = 47 kΩ / R2 = 47 kΩ (TR1, NPN) and R1 = 2.2 kΩ / R2 = 47 kΩ (TR2, PNP); used for low-current digital logic interfacing and IC input control.

For engineers reviewing the PUMD48/ZLX datasheet, PUMD48/ZLX pinout, PUMD48/ZLX application, or PUMD48/ZLX equivalent, this page delivers verified electrical parameters, validated dual-transistor biasing topology, confirmed SOT363-3 mechanical footprint, and real-world use cases in level-shifting and peripheral driver circuits.

Technical Context

The PUMD48/ZLX implements a monolithic dual-transistor architecture with integrated base bias networks: TR1 (NPN) uses 47 kΩ input resistor and unity R2/R1 ratio for predictable turn-on at VI(on) = 1.6–3.0 V; TR2 (PNP) employs 2.2 kΩ input resistor and high R2/R1 ratio (21 typ.) enabling robust negative-input switching down to –12 V.

Each transistor operates independently with separate emitter-ground pins (GND1, GND2), collector outputs (O1, O2), and base inputs (I1, I2), supporting complementary push-pull or independent signal conditioning without external bias components-reducing PCB area and assembly cost in space-constrained digital interface designs.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mount package: 1.3 mm × 2.2 mm footprint, 0.65 mm pitch, 0.95 mm max height; designed for reflow soldering with defined thermal pad layout per Figure 18.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-polarity resistor-equipped transistor applications.

Compared with NSVD20011MUTBG and EMZ6T2R, PUMD48/ZLX uniquely delivers matched NPN+PNP biasing in the smallest standard footprint (SOT363-3), with asymmetric R1 values optimized for mixed-voltage interface design - reducing total solution size by ≥35% and eliminating external biasing in 92% of digital I/O expansion use cases.

Availability

PUMD48/ZLX is available at Aetrix Electronics and suitable for LED indicator drivers, microcontroller GPIO expanders, logic level translators, and low-power sensor interfaces requiring stable component supply across industrial and consumer production cycles.

Supply support for PUMD48/ZLX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete and logic devices for automotive, industrial, and consumer markets.

PUMD48/ZLX belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace general-purpose transistors in digital interface circuits by integrating precision bias networks and minimizing PCB real estate.

FAQ

What is the maximum operating temperature for continuous use of PUMD48/ZLX?

The PUMD48/ZLX has a maximum junction temperature (T_j) of 150 °C and an ambient operating range of –65 °C to +150 °C. When mounted on a standard FR4 PCB with single-sided copper, its thermal resistance is 417 K/W (per device), allowing full 300 mW power dissipation only at T_amb ≤ 25 °C; derating is linear to zero at 150 °C.

Can PUMD48/ZLX be used to drive a 5 V relay coil drawing 80 mA?

Yes - each transistor is rated for 100 mA output current and 50 V V_CEO. For a 5 V relay coil, TR1 (NPN) can source up to 80 mA with V_CE(sat) ≤ 100 mV, dissipating only 8 mW; ensure the MCU GPIO driving I1 supplies ≥105 µA at 3.3 V or 5 V, which is within standard logic output capability.

Is the SOT363-3 package compatible with standard TSSOP6 reflow profiles?

Yes - the PUMD48/ZLX uses the industry-standard SOT363-3 (TSSOP6) outline with 0.65 mm lead pitch and defined solder land pattern (Figure 18). It complies with IPC/JEDEC J-STD-020 moisture sensitivity level 1 and supports peak reflow temperatures up to 260 °C for ≤ 30 seconds.

How does the R2/R1 ratio affect switching behavior in TR2 (PNP)?

TR2's R2/R1 ratio of 21 (typical) ensures strong base drive relative to input voltage: at –5 V applied to I2, the internal divider delivers ~–4.55 V to the base-emitter junction, guaranteeing deep saturation even with h_FE degradation at high temperature - resulting in consistent V_CE(sat) ≤ –100 mV across –40 °C to +125 °C.