Nexperia USA Inc. PUMH10,115

Overview

PUMH10 from Nexperia is an NPN/NPN resistor-equipped double transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V V_CEO, 100 mA output current per transistor, with built-in bias resistors R1 = 2.2 kΩ and R2 = 47 kΩ. It functions as a dual digital switching element for low-current logic interfacing and peripheral driver applications in space-constrained PCBs.

For engineers reviewing the PUMH10 datasheet, PUMH10 pinout, PUMH10 application, or PUMH10 equivalent, this device is selected for compact dual-transistor logic-level translation, IC input control, and replacement of discrete BJT pairs where bias network integration reduces layout complexity and assembly cost.

Technical Context

The PUMH10 integrates two matched NPN transistors with monolithically embedded base bias networks-R1 (input resistor) and R2 (feedback resistor)-enabling direct TTL/CMOS-compatible switching without external bias components. Each transistor operates independently with open-base V_CEO = 50 V and I_O = 100 mA rating.

Its internal resistor ratio R2/R1 = 21 (typ.) ensures stable saturation under varying temperature (–40 °C to +150 °C), while h_FE ≥ 100 at I_C = 10 mA and V_CE = 5 V supports reliable digital on/off operation. The device is optimized for surface-mount assembly on FR4 PCBs with standard reflow profiles.

Key Specifications

Pinout & Package

SOT363-3 (SC-88 / TSSOP6) plastic surface-mounted package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height, lead-free and RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual NPN resistor-equipped transistor applications.

Compared with PUMD10 and PUMB10, the PUMH10 is uniquely suited for dual low-side switching applications-its matched NPN pair delivers consistent saturation behavior, lower V_CE(sat), and simplified layout for grounded-load configurations where sourcing capability is unnecessary.

Availability

PUMH10 is available at Aetrix Electronics and suitable for LED driver interfaces, microcontroller GPIO expansion, logic-level translation, and IC input control requiring stable component supply and long-term industrial availability.

Supply support for PUMH10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors-including logic, discretes, MOSFETs, and ESD protection-designed for industrial, automotive, and computing applications.

The PUMH10 belongs to Nexperia's Resistor-Equipped Transistor (RET) product line, engineered specifically to replace discrete BJT-resistor combinations in digital interface and peripheral driver circuits while minimizing PCB area and assembly cost.

FAQ

What is the maximum junction temperature and how does it affect continuous operation?

The PUMH10 has a maximum junction temperature (T_j) of 150 °C. At ambient temperatures above 25 °C, power dissipation must be derated per the 417 K/W per-device thermal resistance (R_th(j-a)). For example, at T_amb = 75 °C, maximum allowable P_tot drops to ~200 mW-requiring ≤100 mA total combined current across both transistors with appropriate PCB copper area.

Can PUMH10 be used in linear amplification mode?

No-the PUMH10 is characterized and qualified exclusively for switching operation. Its built-in R1/R2 network fixes the base bias point, and parameters like h_FE and V_CE(sat) are specified only under digital on/off conditions. Linear gain is not guaranteed, and thermal instability may occur outside the recommended switching duty cycle.

How does the R2/R1 ratio impact noise immunity in noisy environments?

The R2/R1 = 21 ratio provides strong negative feedback that raises the effective input impedance and suppresses false triggering from transient noise. With VI(off) ≤ 0.6 V and VI(on) ≥ 0.75 V, the 150 mV hysteresis margin-enhanced by R2's feedback-ensures reliable switching even with ±100 mV noise superimposed on the input signal.

Is the SOT363-3 package compatible with standard SOT363 reflow footprints?

Yes-the SOT363-3 is a refined variant of SOT363 with tighter dimensional tolerances and updated solder land recommendations (e.g., 0.5 mm pad width, 2.35 mm body length). It is mechanically and thermally compatible with legacy SOT363 footprints, though Nexperia recommends using the updated reflow footprint (Fig. 11) for optimal solder joint reliability and voiding control.