Nexperia USA Inc. PUMH13F

Overview

PUMH13F from Nexperia is a dual NPN resistor-equipped transistor (RET) in SOT363-3 (SC-88) package, rated for 50 V V_CEO, 100 mA output current per transistor, with integrated bias resistors R1 = 4.7 kΩ and R2 = 47 kΩ (R2/R1 = 10). It functions as a compact, pre-biased switching pair for digital logic interfacing and low-current peripheral driving in space-constrained PCBs.

For engineers reviewing the PUMH13F datasheet, PUMH13F pinout, PUMH13F application, or PUMH13F equivalent, this page delivers verified electrical parameters, validated dual-transistor pin mapping, confirmed thermal derating behavior on FR4 PCB, and real-world substitution guidance for RET-based logic-level translation circuits.

Technical Context

The PUMH13F integrates two matched NPN transistors with monolithically embedded base bias networks-each featuring a 4.7 kΩ input resistor (R1) and a 47 kΩ feedback resistor (R2)-enabling direct TTL/CMOS-compatible switching without external bias components. Its dual-emitter-grounded configuration supports independent control of two loads from separate logic inputs.

Designed for digital switching-not linear amplification-the device exhibits guaranteed V_CE(sat) ≤ 100 mV at I_C = 5 mA / I_B = 0.25 mA, VI(on) = 0.9–1.3 V, and VI(off) = 0.5–0.6 V, ensuring robust noise margin and fast turn-on/turn-off in 3.3 V and 5 V logic systems.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mounted package: 1.3 mm × 2.2 mm footprint, 0.65 mm pitch, 0.9–1.15 mm height, 6-pin transparent top view with pin 1 index mark.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual NPN resistor-equipped transistor applications.

Compared with PUMD13 (NPN/PNP) and PUMB13 (PNP/PNP), the PUMH13F provides matched dual-NPN switching ideal for parallel low-side loads, offering superior current gain consistency and lower V_CE(sat) than mixed-polarity alternatives in unidirectional drive applications.

Availability

PUMH13F is available at Aetrix Electronics and suitable for LED indicator drivers, microcontroller GPIO expansion, and industrial sensor interface circuits requiring stable component supply, long-lifecycle assurance, and RoHS-compliant SMT assembly.

Supply support for PUMH13F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices optimized for efficiency, miniaturization, and manufacturability in high-volume electronics.

The PUMH13F belongs to Nexperia's Resistor-Equipped Transistor (RET) family-engineered specifically to replace multi-component transistor-resistor networks in digital logic interfacing, reducing design time and improving SMT yield in consumer, industrial, and automotive-adjacent applications.

FAQ

What is the maximum continuous current per channel for PUMH13F?

The PUMH13F supports 100 mA DC output current per transistor under T_amb ≤ 25 °C with derating to zero at 150 °C junction temperature. At 70 °C ambient, maximum sustainable current is ~65 mA per channel based on its 417 K/W thermal resistance and 300 mW total device power limit.

Can PUMH13F be used in 3.3 V logic systems without level shifting?

Yes-its VI(on) range of 0.9–1.3 V and VI(off) of 0.5–0.6 V ensures full compatibility with 3.3 V CMOS outputs. The internal R1 resistor draws ~0.7 mA from a 3.3 V driver, well within standard GPIO sink capability, and guarantees saturation down to 2.7 V supply.

Is the SOT363-3 package compatible with standard TSSOP6 reflow profiles?

Yes-the PUMH13F uses the industry-standard SOT363-3 (TSSOP6) footprint with 0.65 mm pitch and defined solder land dimensions (2.35 × 0.4 mm per pad). It complies with IPC-7351B density level A and supports J-STD-020D reflow profiles including peak temperatures up to 260 °C.

How does the R2/R1 ratio affect switching behavior?

The fixed R2/R1 = 10 ratio provides negative feedback that stabilizes the base current against transistor β variation and temperature drift. This ensures consistent V_CE(sat) and prevents thermal runaway during sustained conduction-critical for reliability in always-on indicator or enable circuits.