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Home > Products > Discrete Semiconductor Products > Transistors > Bipolar (BJT) > Bipolar Transistor Arrays, Pre-Biased

Nexperia USA Inc. PUMH2/ZLX

Name: PUMH2/ZLX
Brand: Nexperia USA Inc.
SKU: PUMH2/ZLX
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PUMH2/ZLX

Manufacturer:: Nexperia USA Inc.

Category:: Bipolar Transistor Arrays, Pre-Biased

Package:: 6-TSSOP, SC-88, SOT-363

Datasheet:: PUMH2/ZLX.pdf

Description:: TRANS PREBIAS

Quantity:: RFQ Add To RFQ list

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Inventory:4,649

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Product details

Overview

PUMH2/ZLX from Nexperia is a dual NPN resistor-equipped transistor (RET) in SOT363-3 (SC-88) package, integrating two matched 50 V, 100 mA NPN transistors with built-in 47 kΩ input bias resistors (R1 = R2) per channel. It functions as a compact, pre-biased digital switch for low-current logic interfacing and peripheral control in space-constrained PCBs.

For engineers reviewing the PUMH2/ZLX datasheet, PUMH2/ZLX pinout, PUMH2/ZLX application, or PUMH2/ZLX equivalent, this device is selected for its integrated bias network, dual-channel symmetry, guaranteed 50 V V_CEO, 100 mA I_O, and validated performance across −40 °C to +150 °C ambient range in industrial control and portable electronics.

Technical Context

The PUMH2/ZLX implements two independent NPN RETs sharing no internal connection between channels-each with identical R1/R2 = 1 ±20% bias networks enabling direct TTL/CMOS-level drive without external base resistors. Its architecture eliminates discrete biasing components while maintaining full DC current gain (h_FE ≥ 80 at I_C = 5 mA) and low saturation voltage (V_CE(sat) ≤ 150 mV at I_C = 10 mA, I_B = 0.5 mA).

Thermal design is supported by per-device R_th(j-a) = 417 K/W on FR4 PCB and total power dissipation up to 300 mW at T_amb = 25 °C. The device operates reliably within −65 °C to +150 °C storage and ambient ranges, with junction temperature limited to 150 °C.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CEO	50 V - Maximum safe collector-emitter voltage before breakdown; enables use in 24 V industrial bus interfaces.
I_O	100 mA - Continuous output current per transistor; sufficient for driving LEDs, small relays, or logic inputs.
R1 / R2	47 kΩ ±28% - Integrated base bias resistors eliminate need for external components and reduce BOM count.
h_FE	≥80 - Minimum DC current gain at 5 mA collector current; ensures reliable switching with low drive current.
V_CE(sat)	≤150 mV - Low saturation voltage minimizes power loss and self-heating in high-duty-cycle switching.
f_T	230 MHz - Transition frequency supports fast digital switching up to ~10–20 MHz edge rates.
C_c	2.5 pF - Collector capacitance limits high-frequency crosstalk and improves noise immunity in mixed-signal layouts.

Pinout & Package

Package: SOT363-3 (SC-88), 6-pin TSSOP surface-mount plastic package with 0.65 mm pitch, 2.2 mm × 1.35 mm footprint, and thermal pad-compatible layout per JEDEC MO-203-AB.

Pin/Terminal	Circuit Role	Design Meaning
1	GND1	Emitter terminal of TR1; connects to system ground reference for first transistor channel.
2	I1	Base input of TR1; accepts logic-level signals (VI(on) = 1.6–3.0 V) with built-in R1 biasing.
3	O2	Collector output of TR2; active-high switched output referenced to V_CC.
4	GND2	Emitter terminal of TR2; independent ground node for second transistor channel.
5	I2	Base input of TR2; electrically isolated from I1; enables independent dual-channel control.
6	O1	Collector output of TR1; provides complementary switched output to O2 with identical specs.

Key Features

Feature	Design Value
Dual independent NPN RETs	Two fully isolated 50 V/100 mA transistors in one SOT363-3 package-no shared terminals or internal coupling.
Matched bias network	R1 = R2 = 47 kΩ ±28% per channel; guarantees consistent turn-on thresholds and reduces layout sensitivity.
Reduced component count	Eliminates four external base resistors in typical dual-transistor logic buffer designs.
Industrial temperature range	Specified operation from −40 °C to +150 °C junction temperature; suitable for under-hood or enclosed industrial environments.

Applications

LED Driver Interface

Microcontroller GPIO Expander

Use Scenario: Driving multiple status LEDs from a 3.3 V microcontroller with limited GPIO current capability.

IC Role / Device Role / Timing Role: Dual-channel level-shifting switch translating MCU logic outputs to 5 V/24 V LED anode supplies.

Use Value: Enables direct drive of up to two 20 mA LEDs per channel without external resistors or level shifters.

Use Scenario: Extending I/O count on resource-constrained MCUs in smart sensor nodes.

IC Role / Device Role / Timing Role: Digital buffer and signal conditioner for adding interrupt-capable inputs or PWM-controlled outputs.

Use Value: Reduces PCB area by 40% vs. discrete transistor+resistor solutions while improving assembly yield.

Logic-Level Translator

Low-Power Peripheral Control

Use Scenario: Interfacing 1.8 V FPGA I/O banks to 5 V legacy peripherals like encoders or optocouplers.

IC Role / Device Role / Timing Role: Bidirectional voltage translation via open-collector configuration with pull-up on output side.

Use Value: Supports clean 10 ns rise/fall times (per f_T = 230 MHz) without added propagation delay.

Use Scenario: Controlling sleep-mode peripherals (e.g., sensors, EEPROMs) in battery-powered IoT devices.

IC Role / Device Role / Timing Role: Low-quiescent-current enable switch with <100 nA leakage (ICBO) in off-state.

Use Value: Cuts standby current by >95% compared to standard BJT buffers due to integrated bias isolation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual NPN RET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
PUMB2	PNP/PNP complement; same package and bias values but opposite polarity; V_CEO = 50 V, I_O = 100 mA.	Required where active-low switching or high-side load control is needed instead of low-side sink.	Select when sourcing current from V_CC is required; not interchangeable without circuit redesign.
PUMD12	NPN/PNP configuration; asymmetric channel types; R1 = 22 kΩ, R2 = 47 kΩ; V_CEO = 50 V, I_O = 100 mA.	Suitable for push-pull output stages or complementary logic buffering where both polarities are needed.	Choose only if mixed-polarity drive is essential; requires separate bias analysis per channel.

Compared with PUMB2 and PUMD12, the PUMH2/ZLX offers symmetrical dual-NPN functionality ideal for parallel low-side switching, simplifying layout and reducing validation effort in single-polarity digital interface designs.

Availability

PUMH2/ZLX is available at Aetrix Electronics and suitable for industrial control panels, portable instrumentation, and consumer electronics requiring stable component supply with guaranteed long-term availability through 2030.

Supply support for PUMH2/ZLX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.

The PUMH2/ZLX belongs to Nexperia's Resistor-Equipped Transistor (RET) family, engineered to replace discrete BJT-resistor combinations in digital logic interface and peripheral driver applications with minimal footprint and maximum manufacturability.

FAQ

What is the maximum operating temperature for PUMH2/ZLX?

The PUMH2/ZLX has a maximum junction temperature of 150 °C and is rated for continuous operation from −40 °C to +150 °C ambient when mounted on a standard FR4 PCB with specified copper area. Derating begins above 25 °C ambient per the 417 K/W thermal resistance curve.

Can PUMH2/ZLX be used in analog amplifier configurations?

No-PUMH2/ZLX is designed exclusively for digital switching applications. Its integrated bias resistors fix the base current path, preventing adjustable biasing required for linear amplification. The datasheet specifies only switching parameters (V_CE(sat), h_FE min, VI(on)/VI(off)), not small-signal gain or linearity metrics.

Is there a lead-free and RoHS-compliant version of PUMH2/ZLX?

Yes-PUMH2/ZLX is manufactured in full compliance with RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006. The SOT363-3 package uses lead-free matte tin terminations and halogen-free molding compound, certified per Nexperia's material declarations.

How does the R2/R1 ratio affect switching behavior?

The R2/R1 ratio of 1.0 ±0.2 sets the internal feedback path that stabilizes the transistor's on-state and defines the effective input impedance. A ratio near unity ensures predictable VI(on) (~1.6–3.0 V) and prevents latch-up or oscillation during fast edge transitions, especially critical in noisy industrial environments.

PUMH2/ZLX Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: -

Package/Case:: 6-TSSOP, SC-88, SOT-363

Packaging:: Bulk

Product Status:: Obsolete

Transistor Type:: 2 NPN - Pre-Biased (Dual)

Current - Collector (Ic) (Max):: 100mA

Voltage - Collector Emitter Breakdown (Max):: 50V

Resistor - Base (R1):: 47kOhms

Resistor - Emitter Base (R2):: 47kOhms

DC Current Gain (hFE) (Min) @ Ic, Vce:: 80 @ 5mA, 5V

Vce Saturation (Max) @ Ib, Ic:: 150mV @ 500µA, 10mA

Current - Collector Cutoff (Max):: 1µA

Frequency - Transition:: 230MHz

Power - Max:: 300mW

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 6-TSSOP

PUMH2/ZLX FAQ

1.How can I place an order for PUMH2/ZLX through Aetrix?

Please submit a Request for Quotation (RFQ) for PUMH2/ZLX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PUMH2/ZLX reliable?

The price and inventory of PUMH2/ZLX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUMH2/ZLX is usually 5 days.

3.What payment methods are accepted for PUMH2/ZLX?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUMH2/ZLX transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PUMH2/ZLX?

PUMH2/ZLX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PUMH2/ZLX order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PUMH2/ZLX?

For technical support, including PUMH2/ZLX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUMH2/ZLX requirements.

6.How does Aetrix verify that PUMH2/ZLX is sourced from the original manufacturer or authorized distributors?

All PUMH2/ZLX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUMH2/ZLX meets industry standards.

7.What is the process for return or replacement of PUMH2/ZLX?

All PUMH2/ZLX units undergo pre-shipment inspection (PSI). If there is an issue with PUMH2/ZLX, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PUMH2/ZLX part is unused and in its original packaging.

Return procedure for PUMH2/ZLX:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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